ANTENNA DESIGN

A schematic diagram of the diamond microstrip patch antenna in a very Sierpinski carpet kind is shown in Figure 1.5. A scaling factor of δ = 1/3 was chosen to maintain the perfect geometry symmetry of fractal structure. A diamond-shaped structure of dimensions 50 mm × 50 mm has been designed. With the scaling factor of 2.5, again a diamond-shaped structure with dimen- sions of 20 mm × 20 mm has been designed and iterated on the existing main diamond structure. This is the first iteration. During the second iteration, four diamond shapes of dimensions 8 mm × 8 mm have been designed and iterated on the main diamond structure. In the third iteration, eight more diamond shapes of dimensions 4 mm × 4 mm have been designed and iter- ated. The substrate used to design the proposed fractal antenna is FR-4 of thickness d = 1.6 mm with relative permittivity εr = 4.4.

Two-element Sierpinski diamond antenna array with quarter-wave feed network is designed and fabricated with the design equations and is shown in Figures 2.5 and 2.6, respectively (Table 2.1).2 Simulated and practical results such as reflection coefficient, voltage standing wave ratio (VSWR), and gain are observed in Figures 2.7–2.11, respectively (Table 2.2).3

DESIGN OF FEED NETWORK FOR AN ARRAY

In the farthest communications, antennas with high directivity are regularly required. Single element antenna is not suitable for high gain or high direc- tivity. High gain can be achieved by an assemblage of antennas, called an array. In the construction of an array, feed network design is essential. Feed network is used in an array to regulate the amplitude and phase of the radi- ating elements to control the beam scanning properties. Thus, in selecting and optimizing the feed network, the design of an array is crucial. Different types of feed networks are series feed, parallel feed, T-split power divider, quarter-wave transformer, and mitered bend feed.

The transmission lines such as coaxial cables, strip lines, and microstrip lines are used in making most feed networks. Impedance matching is vital for ensuring efficient power transfer through feed network. The use of quarter- wave transformer is the best solution for achieving impedance matching. The reflection coefficient between two impedances Z1 and Z3 is cut down by a matching circuit. The quarter-wave transformer shown in Figure 2.2 is one of the most commonly used matching circuits. At the center frequency, a section of transmission line λ/4 (the quarter-wave transformer) long placed between the two transmission lines eliminates the reflection coefficient if its impedance is Z ZZ 2 13 =

SIMULATION RESULTS

To validate the proposed transmission technique, simulations were carried out and the results are presented in this section. Simulations were carried out on MATLAB. The PU source and destination are located at (4, 40) and (500, 40). The two active SUs are located at (200, 20) and (400, 20). The five idle SUs are located at (100, 40), (200, 40), (250, 40), (300, 40), and (400, 40). The scenario we considered assumes the power of PU source PPT = 10 dB and the power of active secondary transmitter is PST1 = PST2 = 10 dB. Link gain α and path loss factor n are taken as (0.097/d2 )1/2 and 2. To prevent the loss of generality, we assume 2 2 2 2 13 10 σσσσ pjk − = = = = . Figure 12.1 presents the simulation model of the system; it presents the five idle SUs, two active SUs, and PU source and destination. We consider the scenario presented in Figure 12.1, where there are five idle SUs, two active SUs, and a PU sender and receiver. The figure helps to identify the distances between the nodes. Figure 12.2 shows the spectrum allocation of the five available channels from SU relay to PU receiver. The figure helps to find the spectral distances between the channels. Bandwidth of the PU channel is 2 MHz and the bandwidth of relay channels is 1 MHz. The performance comparison over the direct path and relayed path by using the different transmission schemes is shown in Figure 12.3. The capacity is plotted by varying the interference threshold and the power of PU transmitter is fixed at 10 dB. Since there is no effect of varying interference threshold17 on overlay transmission and direct path, the capacity response of them is flat. The response with partial relay selection is represented with a dotted line and the response of opportunistic relay selection is represented with a straight line. Figure 12.3 shows that the capacity over the relayed path, chosen by using partial relay selection, gives better performance than the path chosen by using opportunistic relay selection. When the interfer- ence threshold is less than 3 mW, overlay transmission gives better capacity than the proposed scheme. From Figure 12.3, it is evident that the proposed scheme gives good performance than the traditional overlay and underlay techniques at an interference threshold Ith ≥ 3 mW, with the relayed path selected using partial relay selection.

A novel hybrid overlay/underlay strategy for PU throughput maximization is presented. We have analyzed two different relay selection schemes. An algo- rithm to allocate various resources in such hybrid CR scheme is presented. We have shown from the simulations that the proposed hybrid overlay/ underlay technique has better performance over the traditional overlay and underlay techniques. The throughput achieved by the use of the proposed technique is higher than the throughput achieved on the direct path. This is a very useful incentive for the licensed users to cooperate with the unlicensed users. We have also presented the performance of the two relay selection criteria. The partial relay selection is preferable up to the PU transmission of 10 dB. Beyond 10 dB, opportunistic relay selection gives best performance. The opportunistic relay selection has good performance at high SNR, but it is complex, as it needs the channel state info of the first hop. Partial relay selection is more preferable, as it is simple and the usual transmission power level of PU is commonly 10 dB. At the PU transmission power of 10 dB, the proposed hybrid overlay/underlay transmission scheme gives optimal performance when combined with partial relay selection.

SDR–USRP

USRP is one specific type of SDR in which the baseband operations are configured to run on the host computer, while the front end and high-speed operations such as up-and-down conversions are done in the SDR hardware. USRP-RIO can be considered as an advanced version of the USRP, where RIO has an extra configurable (programmable) field-programmable gate array (FPGA) module; so some (or all) of the time critical/computationally intensive baseband operations can be routed to the FPGA, which differs from the basic USRP device. The basic processing blocks of a USRP are as follows: At the transmitter side, USRP will be interfaced with help of the Ethernet (USRP-RIO was interfaced using PXI) followed by the transmission control block; then, data will be split into I and Q channels; in each of the channels, the data will be first upconverted with the help of digital up converter. Later, the data will be converted to analog with the help of digital to analog converter and then passed through a low-pass filter, and RF conversion is done with the help of mixer and local oscillator. Finally, the transmitted symbols are passed through a transmit amplifier. At the receiver side, the inverse process will be done, that is, first, the received signal is passed through RF amplifier followed by a mixer to convert RF level to IF. Later, a series section of an analog-to-digital converter, digital down conversion, receiver control block, and an Ethernet interface used to connect to a computer. A simple block diagram of USRP is as shown in Figure 13.1.7 In this chapter, the implementation is done on USRP-RIO without the help of FPGA. The specifications of the USRP-2922 and USRP-RIO-2953R used are mentioned in Tables 13.18 and 13.2.9

Orthogonal frequency division multiplexing (OFDM) is a versatile multi- carrier technique, dividing the whole band into a number of narrow-band subchannels. Due to its orthogonal nature of the carriers, it adds additional advantage to the system model improving the performance of the system, combating the multipath fading effects in frequency-selective channels. It is the most used modulation technique in a wide range of recent standards such as digital audio broadcasting, digital video broadcasting, WiFi, and long-term evolution. Software-defined radio (SDR) is defined as “radio in which some or all of the physical layer functions are software defined”.1 This gives the user the flexibility of redefining the functioning of the SDR to the application, which is not possible with traditional hardware-based radios (unless through physical modification, thus increasing the cost). This flexibility and cost-effectiveness have motivated the users to shift to SDR for prototyping and testing of their wireless architectures/platforms. The test bed used in this chapter is a universal software radio peripheral (USRP) one of the specific type of SDR, originally developed by Etus Research. USRP developed by National Instruments, the parent company of Etus Research, is becoming the present de facto SDR platform to implement the present transceiver system. The development of the OFDM architecture that is suitable for imple- mentation on USRP2 boards was investigated in Ref. [2]. In brief, this chapter focuses on the Gnu’s Not Unix (GNU) radio implementation of the physical layer of long-term evolution-advanced with simple subcar- rier blinding algorithm which is used to reduce the block error rate. The MATLAB implementation of secondary user cognitive link on SDR/USRP was proposed in Ref. [3] with more generic algorithms to improve the overall performance of the OFDM system. More specifically, the performance is studied in terms of channel estimation, time synchronization, and frequency offset compensation. Ref. [4] introduced more generic OFDM system, in which authors quantified the quality of service in terms of packet-received ratio (PRR) using GNU radio for USRP link and C++ for processing the data. Frequency offset errors using Simulink/MATLAB for the signal processing is investigated in Ref. [5]. A LabVIEW-based implementation of basic OFDM system using USRP2 as the test bed is investigated in Ref. [6], evaluating the performance in indoor wireless channels. In this chapter, the focus is on developing an architecture of OFDM and testing the same on a USRP platform. In today’s data-centric world, most of the data transmitted is in terms of the packets; thus, PRR is the best quantifier to evaluate the performance of the data communications system, so this chapter has taken PRR as the performance measure. This chapter is structured as follows. Section 13.2 gives an overview of the SDR/USRP followed by Section 13.3 giving the implementation details. These will be followed by the results in Section 13.4 and conclusions and future work in Section 13.5.

BASIC ARCHITECTURE OF PRESTO GENERATOR

To test integrated circuits and systems, pseudorandom BIST generators are used. The collection of pseudorandom generators includes LFSRs, cellular automata, and accumulators controlled by a constant value. A large number of random patterns have to be generated for the circuits to hard-to-detect faults. Later, high fault coverage pattern generators are achieved. Generally, we use clock-gating method; two nonoverlapping clocks control the even and odd scan cells of the scan chain to reduce the shift power dissipation. To reduce the switching activities in scan chain, a pseudorandom BIST scheme was proposed. To detect the faults, we require extra test hardware to store additional deterministic test patterns or by inserting test point into the mission logic. To avoid this problem, an accumulator-based weighted pattern generator technique was introduced. This technique uses one of three weights for test patterns namely 0, 1, and 0.5; therefore, it reduced test application time in accumulator-based test pattern generation.2 In this chapter, we propose a PRPG for BIST applications. By using PRESTO levels, we are reducing the switching activity of the generator during scan loading. To reduce the test power, we applying each pattern generated a vector to each PRPG output, which can minimize the input transi- tion, and the number of distinct patterns in a sequence meets the requirement of fault coverage for CUT and the sequence does not contain any repeated

patterns. The conventional algorithm of changing the test vectors produced by LFSR contains extra hardware to get more correlated test vectors with a low number of transitions; they reduce the randomness in the patterns but having lower fault coverage and higher test time.4 The linear relations are selected from a pattern or consecutive vectors, which is the benefit of using sequential decompressor to generating a sequence. Hence, the proposed test pattern generator (TPG) can be easily implemented by hardware. An n-bit PRPG is connected with a phase shifter feeding scan chain from a kernel of the generator producing the actual pseu- dorandom test patterns. A PRPG is implemented by using ring generator or LFSR. n-Hold latches are used between the PRPG and phase shifter. An n-bit toggle control register is controlling each stage of the individual latch as shown in Figure 15.2. Latch that enables input is asserted, the given latch is transparent for data going from the PRPG to the phase shifter, and it said to be in toggle mode. When it disables, it captures and saves, for a number of clock cycles, the corresponding bit of PRPG, thus feeding the phase shifter with a constant value. It is now in the hold mode. It is worth noting that each phase shifter output is obtained by XOR-ing outputs of three different hold latches. Therefore, every scan chain remains in a low- power mode provided only disabled hold latches drive the corresponding phase shifter output. The contents of toggle registers are zeros (0s) and ones (1s). 1s indicate latches in the toggle mode, thus transparent for data. Their fraction deter- mines a scan switching activity. The control register is reloaded once per pattern with shift register content. The enable signals injected into the shift register are produced in a probabilistic fashion. Using the original PRPG with a programmable set of weights, the weights are determined by four AND gates producing 1s with the probability of 0.5, 0.25, 0.125, and 0.0625, respectively. The OR gate allows choosing of probabilities beyond simple powers of 2. A 4-bit register switching is used to activate AND gates and allows selecting a user-defined level of switching activity. For example, if the switching code is 0100, 25% of the control register will set to 1, and thus 25% of hold latches will be enabled. Given the phase shifter structure, one can assess that the amount of scan chains receives constant values and thus the expected toggling ratio. An additional 4-input NOR gate detects the switching code 0000, which will switch the LP functionality off. Note that when working in the weighted random mode, the switching level selector ensures statistically the stable content of the control register in terms 1s it carries. As a result, the same fraction of scan chains will stay in the LP mode even when low toggling chains will keep changing from one test pattern to another. It will correspond to a certain level of toggling in the scan chains.

FULLY OPERATIONAL PRESTO GENERATOR

This section presents additional features that make the PRESTO generator fully operational in a wide range of desired switching rate. This approach splits up a shifting period of every test pattern into a sequence of alternating hold and toggle intervals. We use a T-type flip-flop to move the generator back and forth between these two intervals. T flip-flops switch whenever there is a 1 on its input data. If it is set to 0, the generator enters the hold period with all latches temporarily disabled. This is accomplished by placing AND gates on the control register outputs which will allow freezing of all phase shifter inputs. Only a single scan chain crosses a given core. Its abnormal toggling may cause unacceptable heat dissipation that can only be reduced due to temporary hold periods. If the T flip-flop is set to the toggling period, then the latches enabled by the control register can pass data moving from the PRPG to the scan chains. Two additional parameters kept in hold and toggle registers determine how long the entire generator remains either in the hold mode or in the toggle mode. To terminate from modes, a 1

must occur on the T flip-flop input.3 This weighted pseudorandom signal is produced similarly to that of weighted logic used to feed the shift register. The T flip-flop also controls four 2-input multiplexers routing data from the toggle and hold registers as shown in Figure 15.3. It allows selecting a source of control data that will be used in the next cycle to possibly change the operational mode of the generator.4

Aurther

T. Kishore Kumar, PhD

SRavi Kumar Jatoth, PhD

V. V. Mani, PhD

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